I have pursued different research interests which broadly fall under the umbrella of computer architecture. This page shares those experiences. Please, feel free to shoot me an email (firstname.lastname@example.org) if you would like to talk about any of these.
Architectures for Secure High-Performance Computing
High performance computing (HPC) is moving away from traditional simulation and modeling to large scale computational problems involving large datasets. Sometimes this data can be sensitive, provided by third parties to HPC centers or individual researchers, and raises security concerns. This project aims to provide secure architectures focused on HPC centers keeping the performance loss to minimum.
Related Research Works
SoK: Limitations of Confidential Computing via TEEs for High-Performance Compute Systems, Ayaz Akram, Venkatesh Akella, Sean Peisert, Jason Lowe-Power. IEEE International Symposium on Secure and Private Execution Environment Design (SEED), September 2022. paper Slides
Enabling Design Space Exploration for RISC-V Secure Compute Environments, Ayaz Akram, Venkatesh Akella, Sean Peisert, Jason Lowe-Power. Fifth Workshop on Computer Architecture Research with RISC-V (CARRV 2021), with ISCA 2021. paper
Performance Analysis of Scientific Computing Workloads on General Purpose TEEs, Ayaz Akram, Anna Giannakou, Venkatesh Akella, Jason Lowe-Power and Sean Peisert, 35th IEEE Inter- national Parallel & Distributed Processing Symposium (IPDPS 2021), May, 2021 [arxiv version].
Architectures for Secure High-Performance Computing, Ayaz Akram, Young Architect Workshop (YArch ’21) held in conjunction with the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), April, 2021. [paper] [poster] [video]
Setting up Trusted HPC System in the Cloud, Ayaz Akram, Nov 2020, Blog Post.
Using Trusted Execution Environments on High Performance Computing Platforms, Ayaz Akram, Anna Giannakou, Venkatesh Akella and Jason Lowe-Power and Sean Peisert, In Open-source En- claves Workshop (OSEW 2019), July 2019.
Simulation and Modeling
Computer architects mostly use simulation and modeling techniques to evaluate their research ideas. In the past, I have done comprehensive survey and comparative study of different architectural simulation tools. We also performed some work on showing how to perform more accurate gem5 simulations for x86 targets by exposing some issues with out of order cpu model and showing how to calibrate target configurations to achieve better accuracy.
Currently, I mostly focus on gem5. Recently, I have been contributing to the RISCV support in gem5 and building new DRAM cache models using gem5. I am also involved in a project to build gem5art, a tool for reproducible and structured experiments with gem5 and build gem5-resources to help researchers set-up their gem5 experiments in a short time.
Related Research Works
Analyzing Google Workload Traces in gem5, Ayaz Akram, Maryam Babaie, Jason Lowe-Power, 5th gem5 Users’ Workshop associated with ISCA, June 2023.
What not to do when simulating large workloads!, Maryam Babaie, Ayaz Akram, Jason Lowe-Power, 5th gem5 Users’ Workshop associated with ISCA, June 2023.
Enabling Design Space Exploration of DRAM Caches in Emerging Memory Systems, Maryam Babaie, Ayaz Akram, Jason Lowe-Power. IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2023), April, 2023.
A Cycle-level Unified DRAM Cache Controller Model for 3DXPoint Memory Systems in gem5, Maryam Babaie, Ayaz Akram, Jason Lowe-Power.
HammerSim: A Tool to Model Rowhammer, Kaustav Goswami, Ayaz Akram, Hari Venugopalan, Jason Lowe-Power. Young Architect Workshop (YArch), colocated with ASPLOS 2023.
Toward High-Fidelity Heterogeneous Memory System Modeling in gem5, Maryam Babaie, Ayaz Akram, Jason Lowe-Power. Workshop on Modeling \& Simulation of Systems and Applications (ModSim), August 2022. [Sudha Award Finalist].
Simulating Trusted Execution Environments in gem5, Workshop on Modeling & Simulation of Systems and Applications (ModSim), August 2021.
Modeling HBM2 Memory Controller, Ayaz Akram, Maryam Babaie, Wendy Elsasser, and Jason Lowe-Power. In gem5 Users Workshop in conjunction with ISCA 2022.
A Cycle-level Unified DRAM Cache Controller Model in gem5, Maryam Babaie, Ayaz Akram, Jason Lowe-Power. 4th gem5 Users’ Workshop associated with ISCA, June 2022.
Enabling Design Space Exploration for RISC-V Secure Compute Environments, Ayaz Akram, Venkatesh Akella, Sean Peisert, Jason Lowe-Power. Fifth Workshop on Computer Architecture Research with RISC-V (CARRV 2021), with ISCA 2021, June 2021.
Enabling reproducible and agile full-system simulation, Bobby Bruce, Ayaz Akram, Hoa Nguyen, Kyle Roarty, Mahyar Samani, Marjan Fariborz, Trivikram Reddy, Matt Sinclair, Jason Lowe-Power, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2021), March, 2021.
Artifact, Reproducibility and Testing Framework for gem5, Ayaz Akram, and et al. In Workshop on Modeling & Simulation of Systems and Applications (ModSim’2020), August 2020.
The gem5 Simulator: Version 20.0+, Jason Lowe-Power, Abdul Mutaal Ahmad, Ayaz Akram, and et al., arXiv preprint, July 2020.
gem5art: Zen and the Art of gem5 Experiments, Ayaz Akram, and et al. In gem5 Users Workshop in conjunction with ISCA 2020, June 2020.
X86 Linux Boot Status on gem5-19, Ayaz Akram, Mar 2020, Blog Post.
Validation of the gem5 Simulator for x86 Architectures, Ayaz Akram, and Lina Sawalha, In IEEE/ACM Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS) in conjunction with Supercomputing Conference (SC19), November 2019.
A Survey of Computer Architecture Simulation Techniques and Tools, Ayaz Akram, and Lina Sawalha, In IEEE Access, May 2019.
FlexCPU: A Configurable Out-of-Order CPU Abstraction, Bradley Wang, Ayaz Akram, and Jason Lowe-Power, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2019.
x86 Computer Architectural Simulators: A Comparative Study, Ayaz Akram and Lina Sawalha, In IEEE 34th International Conference on Computer Design (ICCD), October 2016.
Performance and Power Analysis of Instruction Set Architectures
Contemporary instruction set architectures (ISAs) and their implementations demand a revisit of the famous debate of the role of ISAs in determining the performance and energy consumption of any processor. According to different computer architects, the compiler and microarchitectural innovations have made ISAs ineffective. On contrary, many researchers believe that there is still an important role played by ISAs to determine the performance and energy efficiency of processors. This project studies differences among various ISAs and evaluates applications’ performance and energy efficiency compiled for different ISAs on diverse microarchitectures. Another goal of this project is to use machine learning techniques to correlate observed differences across ISAs to particular microarchitectural/non-microarchitectural events and ISA factors.
Related Research Works
A Study of Performance and Power Consumption Differences Among Different ISAs, Ayaz Akram, and Lina Sawalha, In IEEE 21st Euromicro Conference on Digital System Design (DSD), August, 2019.
A Comparative Study of ISA Multimedia Extensions for HPC, Ayaz Akram and Sajjad Rahnama, ECS-201C Project Report, Spring 2019, UC Davis.
A Study on the Impact of Instruction Set Architectures on Processors Performance, Ayaz Akram, Master’s Thesis. Url: https://scholarworks.wmich.edu/masters_theses/1519.
The Impact of ISAs on Performance, Ayaz Akram and Lina Sawalha, In 14th Annual Workshop on Duplicating, Deconstructing, and Debunking (WDDD) in conjunction with ISCA-44, June 2017.
Microarchitectural Side Channel Attacks
Related Research Works
WHISPER A Tool for Run-time Detection of Side-Channel Attacks, M Mushtaq, J Bricq, MK Bhatti, Ayaz Akram, V Lapotre, G Gogniat, P Benoit, In IEEE Access, May 2020.
Meet the Sherlock Holmes of Side Channel Leakage: A Survey of Cache SCA Detection Techniques, Ayaz Akram, M Mushtaq, MK Bhatti, V Lapotre, G Gogniat, In IEEE Access, April 2020.
Sherlock Holmes of Cache Side-Channel Attacks in Intel’s x86 Architecture, Maria Mushtaq, Ayaz Akram, Muhammad Khurram Bhatti, Usman Ali, Vianney Lapotre, and Guy Gogniat, In IEEE Conference on Communications and Network Security (CNS), June 2019.
Machine Learning For Security: The Case of Side-Channel Attack Detection at Run-time, Maria Mushtaq, Ayaz Akram et al, In Proceedings of 25th IEEE International Conference on Electronics Circuits and System (ICECS), December 2018.
Run-time Detection of Prime+Probe Side-Channel Attack on AES Encryption Algorithm, Maria Mushtaq, Ayaz Akram et al, In Proceedings of Global Information Infrastructure and Networking Symposium (GIIS), October 2018.
NIGHTs-WATCH: A Cache-based Side-channel Intrusion Detector Using Hardware Performance Counters, Maria Mushtaq, Ayaz Akram et al, In Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy (HASP) in conjunction with ISCA- 45, June 2018.
Cache-Based Side-Channel Intrusion Detection using Hardware Performance Counters, Maria Mush- taq, Ayaz Akram et al, In 16th CryptArchi Workshop, Lorient France, June 2018.
Machine Learning for Computer Architecture
Related Research Works
- The Tribes of Machine Learning and the Realm of Computer Architecture, Ayaz Akram, and Jason Lowe-Power, arXiv preprint, December, 2020.
As the pipeline depth increases to extract out more parallelism aggressively, the need for a continuous supply of fetched instructions increases as well. Relying on repeating behavior of instruction stream and pre-fetching instructions before their actual use, is one of the many used techniques to improve memory performance associated to instructions as it helps to reduce the number of Instruction cache misses and can also overlap miss latencies. Different ideas have been proposed to implement these prefetchers. This project involved studying different instruction prefetching techniques (Next line prefetchers, Return Address Stack Based Prefetching, Proactive instruction prefetch) by implementing them in gem5 simulator and comparing them with a newly proposed technique based on benchmark working set signatures. This project uses different workloads from BigData Bench suite.
Related (Preliminary) Work
Phase Based Instruction Prefetcher, Ayaz Akram, ECE5950 Project Report, Fall 2015, WMU.
System Mode Emulation in QEMU for OCTEON MIPS64
System emulation is a better alternative to native testing of applications on embedded hardware in terms of cost, time and management. In this project, we have extended Quick Emulator (QEMU v1.0.1) to support Cavium Octeon MIPS64 processor-based embedded systems. The performance of guest Octeon MIPS64 system is also compared against native using synthetic and applications benchmarks. My specific responsibilities in this project were to provide emulation support for devices like Interrupt Controller, Timers, Console and Ethernet Controller(e1000). I also performed experiments to evaluate and improve the performance of emulated system compared to native hardware system.
Emulating an Octeon MIPS64 based Embedded System on X86 in QEMU, Muhammad Amir Mehmood, Qurrat ul Ain, Ayaz Akram, Abdul Qadeer and Abdul Waheed, In IEEE 19th International Multi-topic Conference (INMIC), December, 2016.
Enabling Green Video Streaming over the Internet of Things
I worked on the embedded systems side of this project i.e. setting up wireless sensor nodes using stm32f4 discovery boards and Contiki OS. I worked on porting Contiki OS to the required platform and also worked on adding wifi support in Contiki for the stm32f4 discovery board based platform.
Android-based ECG monitoring System
This project involves the development of a low power and portable ECG monitoring device based on MSP430 microcontroller and an Android Phone. The motivation behind this project was to provide a reliable solution to cardiovascular patients to help them do an independent ECG analysis. Such solutions are cheap and easy to use in academic settings. The ECG monitoring system based on MSP430 microcontroller was fully integrated with sensing electrodes on the transmitter side. The controller converted the analog signal to a digital signal via an inbuilt analog-to-digital converter, conditioned and filtered it for transmission via a Bluetooth transceiver IC compatible with the MSP430. The real-time data was received by the smartphone and displayed in real-time.
Android Based ECG Monitoring System, Ayaz Akram, Raheel Javed and Awais Ahmad, In International Journal of Science and Research (IJSR), November 2013.
Comparative Study of Edge Detection Techniques
Edge detection in a particular image is one of the basic steps of many image processing algorithms. It is therefore important to check the fidelity of edge detection techniques. This project provided a comparison of different edge detection schemes that fall into three main categories of edge detectors: Gradient-based edge detectors, Laplacian-based edge detectors, and Non-derivative based edge detectors. A quantitative (using Pratts figure of merit) and qualitative (using real-life images) comparison of different edge detection techniques was performed.
Comparison of Edge Detectors, Ayaz Akram and Asad Ismail, In International Journal of Computer Science and Information Technology Research, October 2013. (Journal of Computer Science and Information Technology Research, October 2013.